As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, source synchronous transmission may be used in which a clock signal is transmitted to help recover the data. The clock signal determines when a data signal should be sampled by a receiver's circuits.
The clock signal may transition at the beginning of the time the data signal is valid. The receiver often requires, however, that the clock signal transition during the middle of the time that the data signal is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission source. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase offset from the original clock signal.
FIG. 1 shows a typical source synchronous communication system (100). A data signal is transmitted from circuit A (12) to circuit B (34) on a data path (18). The data signal is generated by a logic circuit (14) and output by a transmitter circuit (16) on the circuit A (12). To aid in the recovery of the transmitted data signal, a clock signal is transmitted on a clock path (20) at a similar time as the data signal. Although not shown, the communication system (100) could also have a path to transmit a data signal from circuit B (34) to circuit A (12) along with an additional clock signal (not shown).
In FIG. 1, a DLL (40) generates a copy of the clock signal from the clock path (20) with a valid state and with a phase offset to be used by other circuits. For example, the DLL (40) outputs the copy of the clock signal with a predetermined phase offset to cause a latch device to sample the data signal. A latch device may be, for example, a flip-flop (38) as shown in FIG. 1. When the copy of the clock signal transitions, the flip-flop (38) samples the output of an amplifier (36) that amplifies the data signal on the data path (18). The latched signal from the flip-flop (38) is provided to other circuits on circuit B (34) as a local data signal (42).
As shown in FIG. 2, a path, i.e., the data path (18) and the clock path (20) shown in FIG. 1, has a frequency characteristic (202) that attenuates a signal dependent on a frequency of the signal. As a frequency content of a signal increases, the attenuation of the path increases. Typically, channel equalization is used to “equalize” the frequency characteristic (202) of the path. Basically, a receiver circuit will use an inverse frequency characteristic (204) to equalize the path. As the frequency content of a signal increases, the receiver increases the gain of the signal to offset the increased attenuation. Ideally, after equalization, the frequency characteristic of the path is a flat line for all frequencies; however, equalization may have any desired frequency characteristic.